Configurable RISC-V core sidesteps cache misses with 128 fetches
Modern CPU performance hinges on keeping a processor’s pipeline fed so it executes operations on every tick of the clock, typically using abundant multi-level caching. However, a crop of cache-busting...
View ArticleRISC-V 64 bit IP for High Performance
RISC-V as an Instruction Set Architecture (ISA) has grown quickly in commercial importance and relevance since its release to the open community in 2015, attracting many IP vendors that now provide a...
View ArticleDeeper RISC-V pipeline plows through vector-scalar loops
Many modern processor performance benchmarks rely on as many as three levels of cache staying continuously fed. Yet, new data-intensive applications like multithreaded generative AI and 4K image...
View ArticleRISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces...
Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP. The company delivers high bandwidth, high performance cores with vector...
View ArticleSemidynamics Shakes Up Embedded World 2024 with All-In-One AI IP to Power...
Semidynamics takes a non-traditional approach to design enablement. Not long ago, the company’s Founder and CEO, Roger Espasa unveiled extreme customization at the RISC-V Summit. That announcement...
View ArticleCEO Interview: Roger Espasa of Semidynamics
Roger Espasa is the CEO and founder of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm)...
View ArticleGazzillion Misses – Making the Memory Wall Irrelevant
Memory Hierarchy and the Memory Wall Computer programs mainly move data around. In the meantime, they do some computations on the data but the bulk of execution time and energy is spent moving data...
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